High-Level Synthesis

Benchmarks archive 2025-07-28

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Datasets archive 2025-07-28

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Most implemented papers archive 2025-07-28

30 shown of 40 papers with code (96 tagged with this task in all), ordered by repositories listed in the archive, not by stars (the archive holds no stars, so PwC's “Social” and “Latest” sorts cannot be reproduced). Papers without a page here are shown as plain text.

• LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
  14 Jul 2018 4 repositories listed
  Recent work has shown that Field-Programmable Gate Arrays (FPGAs) play an important role in the acceleration of Machine Learning applications.
• Allo: A Programming Model for Composable Accelerator Design
  7 Apr 2024 2 repositories listed Syntology ran 13 of 20 samples · 7 unverified
  For the GPT2 model, the inference latency of the Allo generated accelerator is 1.
• Hardware-Efficient Deconvolution-Based GAN for Edge Computing
  18 Jan 2022 2 repositories listed
  Generative Adversarial Networks (GAN) are cutting-edge algorithms for generating new data samples based on the learned data distribution.
• Fast inference of deep neural networks in FPGAs for particle physics
  16 Apr 2018 2 repositories listed
  For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.
• LLM-DSE: Searching Accelerator Parameters with LLM Agents
  18 May 2025 1 repository listed
  Even though high-level synthesis (HLS) tools mitigate the challenges of programming domain-specific accelerators (DSAs) by raising the abstraction level, optimizing hardware directive parameters remains a significant…
• HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
  16 Apr 2025 1 repository listed
  HLS-Eval targets two core tasks: (1) generating HLS code from natural language descriptions, and (2) performing HLS-specific code edits to optimize performance and hardware efficiency.
• Enhancing CuFP Library with Self-Alignment Technique
  24 Mar 2025 1 repository listed
  High-Level Synthesis (HLS) tools have transformed FPGA development by streamlining digital design and enhancing efficiency.
• Design and Implementation of an FPGA-Based Hardware Accelerator for Transformer
  20 Mar 2025 1 repository listed
  Transformer-based large language models (LLMs) rely heavily on intensive matrix multiplications for attention and feed-forward layers, with the Q, K, and V linear projections in the Multi-Head Self-Attention (MHA)…
• Neural Architecture Codesign for Fast Physics Applications
  9 Jan 2025 1 repository listed
  Our method employs neural architecture search and network compression in a two-stage approach to discover hardware efficient models.
• Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)
  2 Dec 2024 1 repository listed
  Our aim for the ML Contest for Chip Design with HLS 2024 was to predict the validity, running latency in the form of cycle counts, utilization rate of BRAM (util-BRAM), utilization rate of lookup tables (uti-LUT),…
• Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis
  25 Oct 2024 1 repository listed
  We propose a more domain-generalizable model structure: a two-level hierarchical Mixture of Experts (MoE), that can be flexibly adapted to any GNN model.
• Learning to Compare Hardware Designs for High-Level Synthesis
  20 Sep 2024 1 repository listed
  HLS relies on pragmas, which are directives inserted into the source code to guide the synthesis process, and pragmas have various settings and values that significantly impact the resulting hardware design.
• rule4ml: An Open-Source Tool for Resource Utilization and Latency Estimation for ML Models on FPGA
  9 Aug 2024 1 repository listed
  However, developing ML models for FPGAs is time-consuming, as optimization requires synthesis to evaluate FPGA area and latency, making the process slow and repetitive.
• Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation
  25 Jul 2024 1 repository listed
  Kolmogorov-Arnold Networks (KANs), a novel type of neural network, have recently gained popularity and attention due to the ability to substitute multi-layer perceptions (MLPs) in artificial intelligence (AI) with…
• CuFP: An HLS Library for Customized Floating-Point Operators
  18 Jul 2024 1 repository listed
  High-Level Synthesis (HLS) tools have revolutionized FPGA application development by providing a more efficient and streamlined approach, significantly impacting digital design methodologies.
• Deep Inverse Design for High-Level Synthesis
  11 Jul 2024 1 repository listed
  High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging.
• fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library
  10 Jun 2024 1 repository listed
  Machine learning ensembles combine multiple base models to produce a more accurate output.
• SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation
  25 May 2024 1 repository listed
  In this paper, we introduce SynthAI, a new method for the automated creation of High-Level Synthesis (HLS) designs.
• Fast Algorithms for Spiking Neural Network Simulation with FPGAs
  3 May 2024 1 repository listed
  Using OpenCL-based high-level synthesis, we create a number of spiking neural network (SNN) simulators for the Potjans-Diesmann cortical microcircuit for a high-end Field-Programmable Gate Array (FPGA).
• HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  1 May 2024 1 repository listed
  HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis…
• HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis
  29 Apr 2024 1 repository listed
  Graphics Processing Units (GPUs) have become the leading hardware accelerator for deep learning applications and are used widely in training and inference of transformers; transformers have achieved state-of-the-art…
• Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
  23 Apr 2024 1 repository listed
  High-Level Synthesis (HLS) Design Space Exploration (DSE) is a widely accepted approach for efficiently exploring Pareto-optimal and optimal hardware solutions during the HLS process.
• Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
  14 Jan 2024 1 repository listed
  High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming.
• Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference
  23 Dec 2023 1 repository listed
  Experimental results demonstrate our approach can achieve up to 13.
• GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis
  27 Sep 2023 1 repository listed
  In this paper, we propose GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS, containing a software stack for data generation and baseline deployment, and FPGA…
• Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs
  26 Sep 2023 1 repository listed
  High-level synthesis (HLS) aims to raise the abstraction layer in hardware design, enabling the design of domain-specific accelerators (DSAs) like field-programmable gate arrays (FPGAs) using C/C++ instead of hardware…
• INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing
  11 Aug 2023 1 repository listed
  In this work, we introduce INR-Arch, a framework that transforms the computation graph of an nth-order gradient into a hardware-optimized dataflow architecture.
• Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts
  30 May 2023 1 repository listed
  Computer vision researchers are embracing two promising paradigms: Vision Transformers (ViTs) and Multi-task Learning (MTL), which both show great performance but are computation-intensive, given the quadratic…
• DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference
  13 Apr 2023 1 repository listed
  The experiment results demonstrate that DGNN-Booster can achieve a speedup of up to 5.
• HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
  17 Feb 2023 1 repository listed
  Machine Learning (ML) has been widely adopted in design exploration using high level synthesis (HLS) to give a better and faster performance, and resource and power estimation at very early stages for FPGA-based design.

Syntology lines on 1 of the papers shown; no Syntology record for the others (a paper without an arXiv id cannot be joined to the graph, and absence from the graph layer is not a recorded non-run). “Ran” means the sample executed on a synthesized fixture, not that the paper's result was reproduced. Read from the graph 2026-09-24.