Papers › Security Analysis of Tunnel Field-Effect Transistor for Low Power Hardware

Security Analysis of Tunnel Field-Effect Transistor for Low Power Hardware

25 Apr 2017arXiv:1704.07878links table onlyarchive 2025-07-28

Shayan Taheri, Jiann-Shiun Yuan

The archive published only this paper's code-link row. Authors, date and abstract are from arXiv's metadata (CC0), read from the Kaggle arXiv metadata snapshot of 2026-09-12 where its title matched the archive's; the title is the archive's.

Security and energy are considered as the most important parameters for designing and building a computing system nowadays. Today's attacks target different layers of the computing system (i.e. software and hardware). Introduction of new transistor technologies to the integrated circuits design is beneficial, especially for low energy requirements. The new devices have unique features and properties that provide security advantages. However, these properties may come to the aid of an adversary to design stronger attacks. Therefore, the advantages as well as the disadvantages of these technologies need to be well studied. This paper demonstrates the area and power efficiency of the tunnel field-effect transistor (TFET) technology along with analyzing its security aspects.

PaperPDFCode

Code

Repository list and official/mentioned flags are the archive's, frozen 2025-07-28. Reachability, where shown, is from one Syntology probe window (2026-09-16 to 2026-09-18); repositories not probed show nothing. GitHub stars are not tracked.

Code Syntology ran Syntology

Not run by Syntology. Nothing on this page verifies that the listed code works.

Results from the paper archive 2025-07-28

No leaderboard rows for this paper in the archive.

Report a problem or propose a change · a person checks every report against the paper or source before anything changes; decisions are listed on /corrections