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PERC: Posit Enhanced Rocket Chip
Arunkumar M Vaidyanathan, Sai Ganesh Bhairathi, Harshal Ganpatrao Hayatnagarkar
Balancing between precision and performance is a known trade-off in system design. Universal Number system attempts to dissolve this trade-off with its flexible arbitrary precision bound within fixed bit length. Its Type-III class, also known as Posits, has been especially introduced to be hardware implementation friendly. Posit is a dynamic floating-point representation that ensures better accuracy and precision using a system that minimizes the number of unusable representations and introduces a higher dynamic range which can serve as a substitute for the IEEE-754 2008 floating-point standard. In this paper, we share our experience with implementation and integration of a Posit Processing Unit (PPU) into the Rocket Chip SoC generator. This PPU replaces the IEEE-754 2008 FPU inside the chip, and supports both of RISC-V ISA floating-point extensions namely 'F' for single precision and 'D' for double precision using 32-bit and 64-bit posits respectively. We discuss various design choices that were available to us and the decisions made in this work. We elaborate our use of Chisel, a Scala embedded hardware construction DSL, to describe our design. Later we observe how various constructs in Chisel help not only to describe a product but also aids the description process in a robust, flexible and efficient manner. We further delve into how the design has been tested using a version of the RISC-V ISA test suite which has been modified for Posit arithmetic numbers. The paper also discusses the scope for future work that can be done, including a posit arithmetic accelerator and higher-level toolchain support for posits.
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