Papers › MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design using Mirror Gates
MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design using Mirror Gates
Evan McKinney, Michael Hatridge, Alex K. Jones
The archive published only this paper's code-link row. Authors, date and abstract are from arXiv's metadata (CC0), read from the Kaggle arXiv metadata snapshot of 2026-09-12 where its title matched the archive's; the title is the archive's.
Building efficient large-scale quantum computers is a significant challenge due to limited qubit connectivities and noisy hardware operations. Transpilation is critical to ensure that quantum gates are on physically linked qubits, while minimizing SWAP gates and simultaneously finding efficient decomposition into native basis gates. The goal of this multifaceted optimization step is typically to minimize circuit depth and to achieve the best possible execution fidelity. In this work, we propose MIRAGE, a collaborative design and transpilation approach to minimize SWAP gates while improving decomposition using mirror gates. Mirror gates utilize the same underlying physical interactions, but when their outputs are reversed, they realize a different or mirrored quantum operation. Given the recent attention to √(iSWAP) as a powerful basis gate with decomposition advantages over CNOT, we show how systems that implement the iSWAP family of gates can benefit from mirror gates. Further, MIRAGE uses mirror gates to reduce routing pressure and reduce true circuit depth instead of just minimizing SWAPs. We explore the benefits of decomposition for √(iSWAP) and √(iSWAP) using mirror gates, including both expanding Haar coverage and conducting a detailed fault rate analysis trading off circuit depth against approximate gate decomposition. We also describe a novel greedy approach accepting mirror substitution at different aggression levels within MIRAGE. Finally, for iSWAP systems that use square-lattice topologies, MIRAGE provides an average of 29.6% reduction in circuit depth by eliminating an average of 59.9f% SWAP gates, which ultimately improves the practical applicability of our algorithm.
Code
Repository list and official/mentioned flags are the archive's, frozen 2025-07-28. Reachability, where shown, is from one Syntology probe window (2026-09-16 to 2026-09-18); repositories not probed show nothing. GitHub stars are not tracked.
Code Syntology ran Syntology
Not run by Syntology. Nothing on this page verifies that the listed code works.
Results from the paper archive 2025-07-28
No leaderboard rows for this paper in the archive.
Report a problem or propose a change · a person checks every report against the paper or source before anything changes; decisions are listed on /corrections