Papers › An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition
An Algorithm for Reversible Logic Circuit Synthesis Based on Tensor Decomposition
Hochang Lee, Kyung Chul Jeong, Daewan Han, Panjin Kim
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An algorithm for reversible logic synthesis is proposed. The task is, for a given n-bit substitution map Pₙ: {0,1}ⁿ →{0,1}ⁿ, to find a sequence of reversible logic gates that implements the map. The gate library adopted in this work consists of multiple-controlled Toffoli gates denoted by CᵐX, where m is the number of control bits that ranges from 0 to n-1. Controlled gates with large m (>2) are then further decomposed into C⁰X, C¹X, and C²X gates. A primary concern in designing the algorithm is to reduce the use of C²X gate (also known as Toffoli gate) which is known to be universal. The main idea is to view an n-bit substitution map as a rank-2n tensor and to transform it such that the resulting map can be written as a tensor product of a rank-(2n-2) tensor and the 2×2 identity matrix. Let 𝒫ₙ be a set of all n-bit substitution maps. What we try to find is a size reduction map 𝒜_(red): 𝒫ₙ →{Pₙ: Pₙ = Pₙ₋₁ ⊗I₂}. %, where Iₘ is the m×m identity matrix. One can see that the output Pₙ₋₁ ⊗I₂ acts nontrivially on n-1 bits only, meaning that the map to be synthesized becomes Pₙ₋₁. The size reduction process is iteratively applied until it reaches tensor product of only 2 ×2 matrices.
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