{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/verithoughts-enabling-automated-verilog-code","title":"VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification","arxiv_id":"2505.20302","date":"2025-05-16","proceeding":null,"authors":["Patrick Yubeaton","Andre Nakkab","Weihua Xiao","Luca Collini","Ramesh Karri","Chinmay Hegde","Siddharth Garg"],"abstract":"This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. 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