{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/perc-posit-enhanced-rocket-chip","title":"PERC: Posit Enhanced Rocket Chip","arxiv_id":null,"date":"2020-05-29","proceeding":"Computer Architecture Research with RISC-V 2020 5","authors":["Arunkumar M Vaidyanathan","Sai Ganesh Bhairathi","Harshal Ganpatrao Hayatnagarkar"],"abstract":"Balancing between precision and performance is a known trade-off in system design. Universal Number system attempts to dissolve this trade-off with its flexible arbitrary precision bound within fixed bit length. Its Type-III class, also known as Posits, has been especially introduced to be hardware implementation friendly. Posit is a dynamic floating-point representation that ensures better accuracy and precision using a system that minimizes the number of unusable representations and introduces a higher dynamic range which can serve as a substitute for the IEEE-754 2008 floating-point standard. In this paper, we share our experience with implementation and integration of a Posit Processing Unit (PPU) into the Rocket Chip SoC generator. This PPU replaces the IEEE-754 2008 FPU inside the chip, and supports both of RISC-V ISA floating-point extensions namely 'F' for single precision and 'D' for double precision using 32-bit and 64-bit posits respectively. We discuss various design choices that were available to us and the decisions made in this work. We elaborate our use of Chisel, a Scala embedded hardware construction DSL, to describe our design. Later we observe how various constructs in Chisel help not only to describe a product but also aids the description process in a robust, flexible and efficient manner. We further delve into how the design has been tested using a version of the RISC-V ISA test suite which has been modified for Posit arithmetic numbers. The paper also discusses the scope for future work that can be done, including a posit arithmetic accelerator and higher-level toolchain support for posits.","url_abs":"https://www.researchgate.net/publication/341786799_PERC_Posit_Enhanced_Rocket_Chip","url_pdf":"https://carrv.github.io/2020/papers/CARRV2020_paper_5_MV.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"perc-posit-enhanced-rocket-chip","repo_url":"https://github.com/arunkmv/perc","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[],"methods":[{"method_slug":"rocket","method_name":"ROCKET"}],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}