{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/opencl-based-fpga-accelerator-for-semi-global","title":"OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors","arxiv_id":null,"date":"2021-09-03","proceeding":"International Conference on Field-Programmable Logic and Applications (FPL) 2021 9","authors":["David Castells-Rufas","Santiago Marco-Sola","Quim Aguado-Puig","Antonio Espinosa-Morales","Juan Carlos Moure","Lluc Alvarez","Miquel Moretó"],"abstract":"An FPGA accelerator for the computation of the semi-global Levenshtein distance between a pattern and a reference text is presented. The accelerator provides an important benefit to reduce the execution time of read-mappers used in short-read genomic sequencing. Previous attempts to solve the same problem in FPGA use the Myers algorithm following a column approach to compute the dynamic programming table. We use an approach based on diagonals that allows for some resource savings while maintaining a very high throughput of 1 alignment per clock cycle. The design is implemented in OpenCL and tested on two FPGA accelerators. The maximum\r\nperformance obtained is 91.5 MPairs/s for 100 × 120 sequences and 47 MPairs/s for 300 × 360 sequences, the highest ever reported for this problem.","url_abs":"https://ieeexplore.ieee.org/document/9556490","url_pdf":"https://www.researchgate.net/profile/David-Castells-Rufas/publication/355256697_OpenCL-based_FPGA_Accelerator_for_Semi-Global_Approximate_String_Matching_Using_Diagonal_Bit-Vectors/links/616d3b05951b3574c65e641f/OpenCL-based-FPGA-Accelerator-for-Semi-Global-Approximate-String-Matching-Using-Diagonal-Bit-Vectors.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"opencl-based-fpga-accelerator-for-semi-global","repo_url":"https://github.com/davidcastells/bpc","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}