{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/non-blocking-programmable-delay-line-with","title":"Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter","arxiv_id":"2105.09183","date":"2021-05-19","proceeding":null,"authors":["Glib Mazin","Aleš Stejskal","Michal Dudka","Miroslav Ježek"],"abstract":"We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23 ns up to 1635 ns with a resolution of 10 ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps/K per a logic primitive. We measured the timing jitter of the delay to be in the range of 7 ps - 165 ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits, and reached the overall dead time of 4 ns - 22.5 ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds excess jitter is acceptable, such as in many advanced photonic networks.","url_abs":"https://arxiv.org/abs/2105.09183v1","url_pdf":"https://arxiv.org/pdf/2105.09183v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"links_only","authors_date_abstract":"arXiv metadata, CC0 1.0 (https://info.arxiv.org/help/license), from the Kaggle arXiv metadata snapshot of 2026-09-12"},"code_links":[{"paper_slug":"non-blocking-programmable-delay-line-with","repo_url":"https://github.com/glebmmazin/delayline","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":1,"framework":"none","reach":null}],"tasks":[],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}