{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/lutnet-rethinking-inference-in-fpga-soft","title":"LUTNet: Rethinking Inference in FPGA Soft Logic","arxiv_id":"1904.00938","date":"2019-04-01","proceeding":null,"authors":["Erwei Wang","James J. Davis","Peter Y. K. Cheung","George A. Constantinides"],"abstract":"Research has shown that deep neural networks contain significant redundancy,\nand that high classification accuracies can be achieved even when weights and\nactivations are quantised down to binary values. Network binarisation on FPGAs\ngreatly increases area efficiency by replacing resource-hungry multipliers with\nlightweight XNOR gates. However, an FPGA's fundamental building block, the\nK-LUT, is capable of implementing far more than an XNOR: it can perform any\nK-input Boolean operation. Inspired by this observation, we propose LUTNet, an\nend-to-end hardware-software framework for the construction of area-efficient\nFPGA-based neural network accelerators using the native LUTs as inference\noperators. We demonstrate that the exploitation of LUT flexibility allows for\nfar heavier pruning than possible in prior works, resulting in significant area\nsavings while achieving comparable accuracy. Against the state-of-the-art\nbinarised neural network implementation, we achieve twice the area efficiency\nfor several standard network models when inferencing popular datasets. We also\ndemonstrate that even greater energy efficiency improvements are obtainable.","url_abs":"http://arxiv.org/abs/1904.00938v1","url_pdf":"http://arxiv.org/pdf/1904.00938v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"lutnet-rethinking-inference-in-fpga-soft","repo_url":"https://github.com/awai54st/LUTNet","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"tf","reach":null},{"paper_slug":"lutnet-rethinking-inference-in-fpga-soft","repo_url":"https://github.com/awai54st/logic-shrinkage","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"tf","reach":{"status":"ok","spdx":"BSD-2-Clause"}}],"tasks":[],"methods":[{"method_slug":"pruning","method_name":"Pruning"}],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":"https://app.syntology.ai/?focus=1904.00938","mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}