{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/leflow-enabling-flexible-fpga-high-level","title":"LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks","arxiv_id":"1807.05317","date":"2018-07-14","proceeding":null,"authors":["Daniel H. Noronha","Bahar Salehpour","Steven J. E. Wilton"],"abstract":"Recent work has shown that Field-Programmable Gate Arrays (FPGAs) play an\nimportant role in the acceleration of Machine Learning applications. Initial\nspecification of machine learning applications are often done using a\nhigh-level Python-oriented framework such as Tensorflow, followed by a manual\ntranslation to either C or RTL for synthesis using vendor tools. This manual\ntranslation step is time-consuming and requires expertise that limit the\napplicability of FPGAs in this important domain. In this paper, we present an\nopen-source tool-flow that maps numerical computation models written in\nTensorflow to synthesizable hardware. Unlike other tools, which are often\nconstrained by a small number of inflexible templates, our flow uses Google's\nXLA compiler which emits LLVM code directly from a Tensorflow specification.\nThis LLVM code can then be used with a high-level synthesis tool to\nautomatically generate hardware. We show that our flow allows users to generate\nDeep Neural Networks with very few lines of Python code.","url_abs":"http://arxiv.org/abs/1807.05317v1","url_pdf":"http://arxiv.org/pdf/1807.05317v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"leflow-enabling-flexible-fpga-high-level","repo_url":"https://github.com/danielholanda/LeFlow","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":1,"framework":"tf","reach":null},{"paper_slug":"leflow-enabling-flexible-fpga-high-level","repo_url":"https://github.com/cristian856/HelloWolrd","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"tf","reach":null},{"paper_slug":"leflow-enabling-flexible-fpga-high-level","repo_url":"https://github.com/cristian856/LeFlow","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"tf","reach":null},{"paper_slug":"leflow-enabling-flexible-fpga-high-level","repo_url":"https://github.com/umutcanaltin/research","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"none","reach":null}],"tasks":[{"task_slug":"machine-learning","task_name":"BIG-bench Machine Learning"},{"task_slug":"high-level-synthesis","task_name":"High-Level Synthesis"},{"task_slug":"translation","task_name":"Translation"}],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}