{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/hardware-optimizations-of-dense-binary","title":"Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory","arxiv_id":"1807.08583","date":"2018-07-20","proceeding":null,"authors":["Manuel Schmuck","Luca Benini","Abbas Rahimi"],"abstract":"Brain-inspired hyperdimensional (HD) computing models neural activity\npatterns of the very size of the brain's circuits with points of a\nhyperdimensional space, that is, with hypervectors. Hypervectors are\n$D$-dimensional (pseudo)random vectors with independent and identically\ndistributed (i.i.d.) components constituting ultra-wide holographic words: $D =\n10,000$ bits, for instance. At its very core, HD computing manipulates a set of\nseed hypervectors to build composite hypervectors representing objects of\ninterest. It demands memory optimizations with simple operations for an e cient\nhardware realization. In this paper, we propose hardware techniques for\noptimizations of HD computing, in a synthesizable VHDL library, to enable\nco-located implementation of both learning and classification tasks on only a\nsmall portion of Xilinx(R) UltraScale(TM) FPGAs: (1) We propose simple logical\noperations to rematerialize the hypervectors on the fly rather than loading\nthem from memory. These operations massively reduce the memory footprint by\ndirectly computing the composite hypervectors whose individual seed\nhypervectors do not need to be stored in memory. (2) Bundling a series of\nhypervectors over time requires a multibit counter per every hypervector\ncomponent. We instead propose a binarized back-to-back bundling without\nrequiring any counters. This truly enables on-chip learning with minimal\nresources as every hypervector component remains binary over the course of\ntraining to avoid otherwise multibit component. (3) For every classification\nevent, an associative memory is in charge of finding the closest match between\na set of learned hypervectors and a query hypervector by using a distance\nmetric. This operator is proportional to [...]","url_abs":"http://arxiv.org/abs/1807.08583v2","url_pdf":"http://arxiv.org/pdf/1807.08583v2.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"hardware-optimizations-of-dense-binary","repo_url":"https://github.com/eardbi/hd-vhdl-library","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":1,"framework":"none","reach":null}],"tasks":[],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}