{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/finn-l-library-extensions-and-design-trade","title":"FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs","arxiv_id":"1807.04093","date":"2018-07-11","proceeding":null,"authors":["Vladimir Rybalkin","Alessandro Pappalardo","Muhammad Mohsin Ghaffar","Giulio Gambardella","Norbert Wehn","Michaela Blott"],"abstract":"It is well known that many types of artificial neural networks, including\nrecurrent networks, can achieve a high classification accuracy even with\nlow-precision weights and activations. The reduction in precision generally\nyields much more efficient hardware implementations in regards to hardware\ncost, memory requirements, energy, and achievable throughput. In this paper, we\npresent the first systematic exploration of this design space as a function of\nprecision for Bidirectional Long Short-Term Memory (BiLSTM) neural network.\nSpecifically, we include an in-depth investigation of precision vs. accuracy\nusing a fully hardware-aware training flow, where during training quantization\nof all aspects of the network including weights, input, output and in-memory\ncell activations are taken into consideration. In addition, hardware resource\ncost, power consumption and throughput scalability are explored as a function\nof precision for FPGA-based implementations of BiLSTM, and multiple approaches\nof parallelizing the hardware. We provide the first open source HLS library\nextension of FINN for parameterizable hardware architectures of LSTM layers on\nFPGAs which offers full precision flexibility and allows for parameterizable\nperformance scaling offering different levels of parallelism within the\narchitecture. Based on this library, we present an FPGA-based accelerator for\nBiLSTM neural network designed for optical character recognition, along with\nnumerous other experimental proof points for a Zynq UltraScale+ XCZU7EV MPSoC\nwithin the given design space.","url_abs":"http://arxiv.org/abs/1807.04093v1","url_pdf":"http://arxiv.org/pdf/1807.04093v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"finn-l-library-extensions-and-design-trade","repo_url":"https://github.com/Xilinx/LSTM-PYNQ","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[{"task_slug":"optical-character-recognition","task_name":"Optical Character Recognition"},{"task_slug":"optical-character-recognition","task_name":"Optical Character Recognition (OCR)"},{"task_slug":"quantization","task_name":"Quantization"}],"methods":[{"method_slug":"bilstm","method_name":"BiLSTM"},{"method_slug":"lstm","method_name":"LSTM"},{"method_slug":"sigmoid-activation","method_name":"Sigmoid Activation"},{"method_slug":"tanh-activation","method_name":"Tanh Activation"}],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"syntology_url":null,"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}