{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/combining-processing-throughput-low-latency","title":"Combining processing throughput, low latency and timing accuracy in experiment control","arxiv_id":"2111.15290","date":"2021-11-30","proceeding":null,"authors":["Chun Kit Lam","Stephan Maka","David Nadlinger","Chris Ballance","Sébastien Bourdeauducq"],"abstract":"We ported the firmware of the ARTIQ experiment control infrastructure to an embedded system based on a commercial Xilinx Zynq-7000 system-on-chip. It contains high-performance hardwired CPU cores integrated with FPGA fabric. As with previous ARTIQ systems, the FPGA fabric is responsible for timing all I/O signals to and from peripherals, thereby retaining the exquisite precision required by most quantum physics experiments. A significant amount of latency is incurred by the hardwired interface between the CPU core and FPGA fabric of the Zynq-7000 chip; creative use of the CPU's cache-coherent accelerator ports and the CPU's event flag allowed us to reduce this latency and achieve better I/O performance than previous ARTIQ systems. The performance of the hardwired CPU core, in particular when floating-point computation is involved, greatly exceeds that of previous ARTIQ systems based on a softcore CPU. This makes it interesting to execute intensive computations on the embedded system, with a low-latency path to the experiment. We extended the ARTIQ compiler so that many mathematical functions and matrix operations can be programmed by the user, using the familiar NumPy syntax.","url_abs":"https://arxiv.org/abs/2111.15290v1","url_pdf":"https://arxiv.org/pdf/2111.15290v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"links_only","authors_date_abstract":"arXiv metadata, CC0 1.0 (https://info.arxiv.org/help/license), from the Kaggle arXiv metadata snapshot of 2026-09-12"},"code_links":[{"paper_slug":"combining-processing-throughput-low-latency","repo_url":"https://git.m-labs.hk/M-Labs/artiq-zynq","is_official":1,"mentioned_in_paper":0,"mentioned_in_github":0,"framework":"none","reach":null},{"paper_slug":"combining-processing-throughput-low-latency","repo_url":"https://git.m-labs.hk/M-Labs/zynq-rs","is_official":1,"mentioned_in_paper":0,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}