{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/caffeinated-fpgas-fpga-framework-for","title":"Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks","arxiv_id":"1609.09671","date":"2016-09-30","proceeding":null,"authors":["Roberto DiCecco","Griffin Lacey","Jasmina Vasiljevic","Paul Chow","Graham Taylor","Shawki Areibi"],"abstract":"Convolutional Neural Networks (CNNs) have gained significant traction in the\nfield of machine learning, particularly due to their high accuracy in visual\nrecognition. Recent works have pushed the performance of GPU implementations of\nCNNs to significantly improve their classification and training times. With\nthese improvements, many frameworks have become available for implementing CNNs\non both CPUs and GPUs, with no support for FPGA implementations. In this work\nwe present a modified version of the popular CNN framework Caffe, with FPGA\nsupport. This allows for classification using CNN models and specialized FPGA\nimplementations with the flexibility of reprogramming the device when\nnecessary, seamless memory transactions between host and device, simple-to-use\ntest benches, and the ability to create pipelined layer implementations. To\nvalidate the framework, we use the Xilinx SDAccel environment to implement an\nFPGA-based Winograd convolution engine and show that the FPGA layer can be used\nalongside other layers running on a host processor to run several popular CNNs\n(AlexNet, GoogleNet, VGG A, Overfeat). The results show that our framework\nachieves 50 GFLOPS across 3x3 convolutions in the benchmarks. This is achieved\nwithin a practical framework, which will aid in future development of\nFPGA-based CNNs.","url_abs":"http://arxiv.org/abs/1609.09671v1","url_pdf":"http://arxiv.org/pdf/1609.09671v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"caffeinated-fpgas-fpga-framework-for","repo_url":"https://github.com/dicecco1/fpga_caffe","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[{"task_slug":null,"task_name":"GPU"},{"task_slug":"classification","task_name":"General Classification"}],"methods":[{"method_slug":"convolution","method_name":"Convolution"},{"method_slug":"dense-connections","method_name":"Dense Connections"},{"method_slug":"dropout","method_name":"Dropout"},{"method_slug":"max-pooling","method_name":"Max Pooling"},{"method_slug":"relu","method_name":"ReLU"},{"method_slug":"softmax","method_name":"Softmax"}],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"syntology_url":null,"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}