{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/annotating-slack-directly-on-your-verilog","title":"Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization","arxiv_id":"2403.18453","date":"2024-03-27","proceeding":null,"authors":["Wenji Fang","Shang Liu","Hongce Zhang","Zhiyao Xie"],"abstract":"In digital IC design, compared with post-synthesis netlists or layouts, the early register-transfer level (RTL) stage offers greater optimization flexibility for both designers and EDA tools. However, timing information is typically unavailable at this early stage. Some recent machine learning (ML) solutions propose to predict the total negative slack (TNS) and worst negative slack (WNS) of an entire design at the RTL stage, but the fine-grained timing information of individual registers remains unavailable. In this work, we address the unique challenges of RTL timing prediction and introduce our solution named RTL-Timer. To the best of our knowledge, this is the first fine-grained general timing estimator applicable to any given design. RTL-Timer explores multiple promising RTL representations and proposes customized loss functions to capture the maximum arrival time at register endpoints. RTL-Timer's fine-grained predictions are further applied to guide optimization in a standard synthesis flow. The average results on unknown test designs demonstrate a correlation above 0.89, contributing around 3% WNS and 10% TNS improvement after optimization.","url_abs":"https://arxiv.org/abs/2403.18453v2","url_pdf":"https://arxiv.org/pdf/2403.18453v2.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"links_only","authors_date_abstract":"arXiv metadata, CC0 1.0 (https://info.arxiv.org/help/license), from the Kaggle arXiv metadata snapshot of 2026-09-12"},"code_links":[{"paper_slug":"annotating-slack-directly-on-your-verilog","repo_url":"https://github.com/hkust-zhiyao/rtl-timer","is_official":1,"mentioned_in_paper":1,"mentioned_in_github":0,"framework":"none","reach":null}],"tasks":[],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":"https://app.syntology.ai/?focus=2403.18453","mcp":{"get_harvested_code_for_paper":{"arxiv_id":"2403.18453"}},"developers":"https://syntology.ai/developers","read_at":"2026-09-24T18:15:14+00:00","read_at_is":"when the build read Syntology's graph, not when any sample ran","claim":"Per-sample execution status on synthesized fixtures; not a correctness claim about the paper. Samples come from repositories linked to the paper, official or community; repo_kind says which.","repos":[{"provenance":"external:paperswithcode_snapshot_2025-07-28","url":"https://github.com/hkust-zhiyao/rtl-timer","reach":null}],"summary":{"ran_honours":1,"ran_draft_wrong":1,"unverified":1},"by_repo_kind":{"official":{"samples":3,"ran":2,"repositories":1}},"repo_kind_vocabulary":{"official":"The archive marks this repository official for the paper","named_in_paper":"The archive records that the paper mentions this repository; it is not marked official","listed":"In the archive's code links for this paper, not marked official and not recorded as mentioned in the paper","found_in_text":"Syntology found this repository in the paper's own text; whether it is the authors' implementation is not asserted","community":"Not in the archive's code links for this paper; a community repository Syntology harvested"},"n_pointer_only_for_licence":0,"samples":[{"code_sha256_prefix":"a6d9884a730e198d","entry":"data_augment","repo":"hkust-zhiyao/rtl-timer","repo_kind":"official","path":"RTL_pwr_model/train_infer_k_fold_BOG.component.py","file_url":"https://github.com/hkust-zhiyao/rtl-timer/blob/HEAD/RTL_pwr_model/train_infer_k_fold_BOG.component.py","link_basis":"first_harvest_node","language":"python","status":"ran_honours","verification_level":1,"contract_check":"HONOURS","metamorphic_tier":"deterministic","behaviour_fingerprint":true,"licence":"BSD-3-Clause","inline_ok":true,"mcp_get_code":{"code_sha256":"a6d9884a730e198d"}},{"code_sha256_prefix":"d26820d0c2d116e7","entry":"testing","repo":"hkust-zhiyao/rtl-timer","repo_kind":"official","path":"RTL_timing_model/train_infer_k_fold_BOG.slack.py","file_url":"https://github.com/hkust-zhiyao/rtl-timer/blob/HEAD/RTL_timing_model/train_infer_k_fold_BOG.slack.py","link_basis":"first_harvest_node","language":"python","status":"ran_draft_wrong","verification_level":1,"contract_check":"OUTPUT_MISDECLARED","metamorphic_tier":null,"behaviour_fingerprint":false,"licence":"BSD-3-Clause","inline_ok":true,"mcp_get_code":{"code_sha256":"d26820d0c2d116e7"}},{"code_sha256_prefix":"420fcb5c05334178","entry":"testing","repo":"hkust-zhiyao/rtl-timer","repo_kind":"official","path":"RTL_pwr_model/train_infer_k_fold_BOG.component.py","file_url":"https://github.com/hkust-zhiyao/rtl-timer/blob/HEAD/RTL_pwr_model/train_infer_k_fold_BOG.component.py","link_basis":"first_harvest_node","language":"python","status":"unverified","verification_level":0,"contract_check":null,"metamorphic_tier":null,"behaviour_fingerprint":false,"licence":"BSD-3-Clause","inline_ok":true,"mcp_get_code":{"code_sha256":"420fcb5c05334178"}}]},"arxiv_metadata":null,"syntology_extracted_results":null}