{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/accelerated-charged-particle-tracking-with","title":"Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs","arxiv_id":"2012.01563","date":"2020-11-30","proceeding":null,"authors":["Aneesh Heintz","Vesal Razavimaleki","Javier Duarte","Gage DeZoort","Isobel Ojalvo","Savannah Thais","Markus Atkinson","Mark Neubauer","Lindsey Gray","Sergo Jindariani","Nhan Tran","Philip Harris","Dylan Rankin","Thea Aarrestad","Vladimir Loncar","Maurizio Pierini","Sioni Summers","Jennifer Ngadiuba","Mia Liu","Edward Kreinar","Zhenbin Wu"],"abstract":"We develop and study FPGA implementations of algorithms for charged particle tracking based on graph neural networks. The two complementary FPGA designs are based on OpenCL, a framework for writing programs that execute across heterogeneous platforms, and hls4ml, a high-level-synthesis-based compiler for neural network to firmware conversion. We evaluate and compare the resource usage, latency, and tracking performance of our implementations based on a benchmark dataset. We find a considerable speedup over CPU-based execution is possible, potentially enabling such algorithms to be used effectively in future computing workflows and the FPGA-based Level-1 trigger at the CERN Large Hadron Collider.","url_abs":"https://arxiv.org/abs/2012.01563v1","url_pdf":"https://arxiv.org/pdf/2012.01563v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"accelerated-charged-particle-tracking-with","repo_url":"https://github.com/jmduarte/GNN_Tracking_FPGA_Neurips20_poster","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"none","reach":{"status":"unanswered"}}],"tasks":[{"task_slug":null,"task_name":"CPU"},{"task_slug":"high-level-synthesis","task_name":"High-Level Synthesis"}],"methods":[],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":"https://app.syntology.ai/?focus=2012.01563","mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}