{"about":{"site":"https://codewithpapers.app","non_affiliation":"Code with Papers and Syntology are not affiliated with, endorsed by, or sponsored by Papers with Code, Meta, or the pwc-archive mirror.","licence":"CC BY-SA 4.0","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","attribution":"https://codewithpapers.app/attribution","modified":"archive material modified by Syntology; see the attribution page"},"url":"/paper/a-design-methodology-for-efficient","title":"A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA","arxiv_id":"1705.02583","date":"2017-05-07","proceeding":null,"authors":["Xin-Yu Zhang","Srinjoy Das","Ojash Neopane","Ken Kreutz-Delgado"],"abstract":"In recent years deep learning algorithms have shown extremely high\nperformance on machine learning tasks such as image classification and speech\nrecognition. In support of such applications, various FPGA accelerator\narchitectures have been proposed for convolutional neural networks (CNNs) that\nenable high performance for classification tasks at lower power than CPU and\nGPU processors. However, to date, there has been little research on the use of\nFPGA implementations of deconvolutional neural networks (DCNNs). DCNNs, also\nknown as generative CNNs, encode high-dimensional probability distributions and\nhave been widely used for computer vision applications such as scene\ncompletion, scene segmentation, image creation, image denoising, and\nsuper-resolution imaging. We propose an FPGA architecture for deconvolutional\nnetworks built around an accelerator which effectively handles the complex\nmemory access patterns needed to perform strided deconvolutions, and that\nsupports convolution as well. We also develop a three-step design optimization\nmethod that systematically exploits statistical analysis, design space\nexploration and VLSI optimization. To verify our FPGA deconvolutional\naccelerator design methodology we train DCNNs offline on two representative\ndatasets using the generative adversarial network method (GAN) run on\nTensorflow, and then map these DCNNs to an FPGA DCNN-plus-accelerator\nimplementation to perform generative inference on a Xilinx Zynq-7000 FPGA. Our\nDCNN implementation achieves a peak performance density of 0.012 GOPs/DSP.","url_abs":"http://arxiv.org/abs/1705.02583v1","url_pdf":"http://arxiv.org/pdf/1705.02583v1.pdf","source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","licence_url":"https://creativecommons.org/licenses/by-sa/4.0/legalcode","row_kind":"abstracts"},"code_links":[{"paper_slug":"a-design-methodology-for-efficient","repo_url":"https://github.com/chl218/DCNN-on-FPGA","is_official":0,"mentioned_in_paper":0,"mentioned_in_github":1,"framework":"none","reach":null}],"tasks":[{"task_slug":null,"task_name":"CPU"},{"task_slug":"denoising","task_name":"Denoising"},{"task_slug":null,"task_name":"GPU"},{"task_slug":"classification","task_name":"General Classification"},{"task_slug":null,"task_name":"Generative Adversarial Network"},{"task_slug":"image-classification","task_name":"Image Classification"},{"task_slug":"image-denoising","task_name":"Image Denoising"},{"task_slug":"scene-segmentation","task_name":"Scene Segmentation"},{"task_slug":"speech-recognition","task_name":"Speech Recognition"},{"task_slug":"super-resolution","task_name":"Super-Resolution"},{"task_slug":"image-classification","task_name":"image-classification"},{"task_slug":"speech-recognition-1","task_name":"speech-recognition"}],"methods":[{"method_slug":"convolution","method_name":"Convolution"}],"datasets_introduced":[],"methods_introduced":[],"results":[],"syntology":{"atlas_url":null,"mcp":null,"developers":"https://syntology.ai/developers"},"arxiv_metadata":null,"syntology_extracted_results":null}