{"url":"/method/squeezenext-block","slug":"squeezenext-block","name":"SqueezeNeXt Block","full_name":"SqueezeNeXt Block","full_name_withheld":false,"description_markdown":"A **SqueezeNeXt Block** is a two-stage bottleneck module used in the [SqueezeNeXt](https://paperswithcode.com/method/squeezenext) architecture to reduce the number of input channels to the 3 × 3 [convolution](https://paperswithcode.com/method/convolution). We decompose with separable convolutions to further reduce the number of parameters (orange parts), followed by a 1 × 1 expansion module.","description_state":"present","introduced_year":null,"introduced_by":{"title":"SqueezeNext: Hardware-Aware Neural Network Design","paper":"/paper/squeezenext-hardware-aware-neural-network","first_author":"Amir Gholami","n_authors":8,"url_abs":null,"archive_paper_url":"https://paperswithcode.com/paper/squeezenext-hardware-aware-neural-network"},"source":{"url":"http://arxiv.org/abs/1803.10615v2","title":"SqueezeNext: Hardware-Aware Neural Network Design","url_on_a_paper_host":true},"code_snippet_url":"https://github.com/osmr/imgclsmob/blob/c03fa67de3c9e454e9b6d35fe9cbb6b15c28fda7/pytorch/pytorchcv/models/squeezenext.py#L14","code_snippet_url_on_a_code_host":true,"categories":[{"area":"Computer Vision","area_id":"computer-vision","collection":"Image Model Blocks","url":"/methods/category/image-model-blocks","pwc_aliases":[]},{"area":"General","area_id":"general","collection":"Skip Connection Blocks","url":"/methods/category/skip-connection-blocks","pwc_aliases":[]}],"n_papers_tagged":3,"archive_num_papers":3,"papers_newest_first":[{"paper":"/paper/190503696","title":"HAWQ: Hessian AWare Quantization of Neural Networks with Mixed-Precision","date":"2019-04-29","arxiv_id":"1905.03696","n_code_links":1,"syntology":{"ran":1,"of":3,"unverified":2,"pointer_only":3}},{"paper":"/paper/anode-unconditionally-accurate-memory","title":"ANODE: Unconditionally Accurate Memory-Efficient Gradients for Neural ODEs","date":"2019-02-27","arxiv_id":"1902.10298","n_code_links":5,"syntology":{"ran":2,"of":7,"unverified":5,"pointer_only":1}},{"paper":"/paper/squeezenext-hardware-aware-neural-network","title":"SqueezeNext: Hardware-Aware Neural Network Design","date":"2018-03-23","arxiv_id":"1803.10615","n_code_links":8,"syntology":{"ran":1,"of":1,"unverified":0,"pointer_only":0}}],"papers_shown":3,"tasks":[{"task":"/task/clustering-multivariate-time-series","name":"Clustering Multivariate Time Series","papers":1},{"task":"/task/multivariate-time-series-imputation","name":"Multivariate Time Series Imputation","papers":1},{"task":"/task/quantization","name":"Quantization","papers":1}],"tasks_shown":3,"n_tasks":3,"usage_by_year":[{"year":"2018","papers":1},{"year":"2019","papers":2}],"row_source":"methods_table","archive":{"source":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28","archive_url":"https://paperswithcode.com/method/squeezenext-block"},"syntology_read_at":"2026-09-24T18:15:14+00:00"}