{"url":"/dataset/verireason-rtl-coder-7b-reasoning-tb-simple","name":"Verireason-RTL-Coder_7b_reasoning_tb_simple","full_name":"Simple Problems of VeriReason Verilog Dataset with Reasoning, Testbench, and Simulation Results","description_markdown":"# [Verireason-RTL-Coder_7b_reasoning_tb_simple](https://huggingface.co/datasets/Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb_simple)\r\n\r\nFor implementation details, visit our GitHub repository: [VeriReason](https://github.com/NellyW8/VeriReason)\r\n\r\nCheck out our paper: [VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation](https://arxiv.org/abs/2505.11849)\r\n\r\n\r\n## Update Log\r\n2025.05.17: Initial release of Nellyw888/Verireason-RTL-Coder_7b_reasoning_tb_simple\r\n\r\n## Project Description\r\nThis study introduces VeriReason, a novel approach utilizing reinforcement learning with testbench feedback to enhance the performance of pre-trained models for Verilog RTL code generation. VeriReason combines supervised fine-tuning with Guided Reward Proximal Optimization (GRPO) reinforcement learning, specifically tailored for RTL code generation. Using our curated high-quality training examples alongside a feedback-driven reward model, VeriReason achieves 83.1% functional correctness on the VerilogEval Machine benchmark, substantially outperforming both comparable-sized models and much larger commercial systems like GPT-4 Turbo.\r\nThe model integrates explicit reasoning capabilities with reinforcement learning for Verilog generation, establishing a new state-of-the-art for automated RTL synthesis. Our 7B parameter model based on Code Llama demonstrates up to a 2.8× increase in first-attempt functional correctness compared to baseline methods and exhibits robust generalization to unseen designs.\r\n\r\n## Installation\r\nTo install this project, follow these steps:\r\n1. Clone the repository: git clone https://github.com/NellyW8/VeriReason.git\r\n2. Navigate to the project directory: cd VeriReason\r\n3. Install the dependencies as specified in the repository\r\n\r\n## Dataset Summary\r\n\r\nVeriReason-RTL-Coder_7b_reasoning_tb is a high-quality dataset for training and evaluating models for Verilog Register-Transfer Level (RTL) code generation with explicit reasoning. The dataset is a curated and enhanced version of the original RTLCoder dataset, specifically designed to improve model reasoning capabilities and functional correctness in RTL code generation.\r\n\r\n## Dataset Creation\r\n\r\n### Source Data\r\n- **Base Dataset**: Built and selected upon the RTLCoder dataset\r\n- **Enhancements**: \r\n  - Added explicit reasoning steps using GPT-4.1\r\n  - Improved code quality to better follow instructions\r\n  - Included testbenches generated with GPT-4.1\r\n  - Incorporated simulation results from running testbenches with the generated code\r\n\r\n## Dataset Structure\r\n\r\n### Data Instances\r\nEach instance in the dataset contains:\r\n- `id`: Unique identifier for the example\r\n- `instruction`: Problem specification for RTL design\r\n- `output`: Generated Verilog code solution\r\n- `tb`: Testbench code for validation\r\n- `tb_result`: Results from running the testbench on the solution\r\n\r\n### Data Fields\r\n- **instruction**: String containing the RTL design problem statement (average length: ~3,973 characters)\r\n- **output**: String containing the Verilog code solution (average length: ~2,024 characters)\r\n- **tb**: String containing the testbench code (average length: ~1,551-12,700 characters)\r\n- **tb_result**: String containing simulation results (average length: ~5,800 characters)\r\n\r\n## Usage Example\r\nTo use this dataset for model training:\r\n\r\n```python\r\nfrom datasets import load_dataset\r\n\r\n# Load the dataset\r\ndataset = load_dataset(\"Nellyw888/Verireason-RTL-Coder_7b_reasoning_tb_simple\")\r\n\r\n# Example of accessing an entry\r\nexample = dataset['train'][0]\r\ninstruction = example['instruction']\r\nreasoning_and_solution = example['output']\r\ntestbench = example['tb']\r\ntest_results = example['tb_result']\r\n```\r\n\r\n## Models Trained Using This Dataset\r\n- [Nellyw888/VeriReason-Qwen2.5-7b-SFT-Reasoning](https://huggingface.co/Nellyw888/VeriReason-Qwen2.5-7b-SFT-Reasoning) - A 7B parameter model based on Qwen2.5-Coder-7B-Instruct, fine-tuned using this dataset with both supervised learning and reinforcement learning techniques.\r\n- [Nellyw888/VeriReason-Qwen2.5-3B-Verilog-RTL-GRPO-reasoning-tb](https://huggingface.co/Nellyw888/VeriReason-Qwen2.5-3B-Verilog-RTL-GRPO-reasoning-tb) - A 3B parameter model based on Qwen2.5-Coder-3B-Instruct, fine-tuned using this dataset with both supervised learning and reinforcement learning techniques.\r\n- [Nellyw888/VeriReason-Qwen2.5-1.5B-grpo-small](https://huggingface.co/Nellyw888/VeriReason-Qwen2.5-1.5B-grpo-small) - A 1.5B parameter model based on Qwen2.5-Coder-1.5B-Instruct, fine-tuned using this dataset with both supervised learning and reinforcement learning techniques.\r\n- [Nellyw888/VeriReason-Llama-7b-RTLCoder-GRPO-reasoning-tb](https://huggingface.co/Nellyw888/VeriReason-Llama-7b-RTLCoder-GRPO-reasoning-tb) - A 7B parameter model based on codellama/CodeLlama-7b-Instruct-hf, fine-tuned using this dataset with both supervised learning and reinforcement learning techniques.\r\n\r\n\r\n## Citation\r\n\r\nPlease cite our paper if you use our model:\r\n\r\n```bibtex\r\n@misc{wang2025verireason,\r\n      title={VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation}, \r\n      author={Yiting Wang and Guoheng Sun and Wanghao Ye and Gang Qu and Ang Li},\r\n      year={2025},\r\n      eprint={2505.11849},\r\n      archivePrefix={arXiv},\r\n      primaryClass={cs.AI},\r\n      url={https://arxiv.org/abs/2505.11849}, \r\n}\r\n```","description_withheld":null,"homepage":"https://huggingface.co/collections/AI4EDA-CASE","introduced_date":"2025-05-17","introduced_date_note":null,"introduced_by":{"paper":"/paper/verireason-reinforcement-learning-with-1","title":"VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation","first_author":"Yiting Wang","url":null},"license":null,"modalities":[{"name":"Texts","url":"/datasets/modality/texts"}],"tasks":[{"name":"Code Generation","url":"/task/code-generation","datasets_with_task":"/datasets/task/code-generation"},{"name":"Text-to-Code Generation","url":"/task/text-to-code-generation","datasets_with_task":"/datasets/task/text-to-code-generation"}],"languages":[{"name":"English","url":"/datasets/language/english"}],"variants":["Verireason-RTL-Coder_7b_reasoning_tb_simple"],"data_loaders":[],"num_papers_in_archive":1,"source":{"archive":"pwc-archive (Hugging Face), CC BY-SA 4.0","snapshot":"2025-07-28"},"benchmarks":[],"papers_with_a_benchmark_row":[],"syntology_totals":{"read_at":"2026-09-24T18:15:14+00:00","papers_with_samples":0,"samples_harvested":0,"samples_ran":0,"samples_unverified":0,"pointer_only_for_licence":0,"papers_with_no_sample_that_ran":0,"note":"the per-paper counts above, summed; not a rate"},"papers_note":"The archive never published its papers-using-dataset list; these are papers with a leaderboard row on this dataset's benchmarks."}